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application the sm3-it timing module is a complete system clock module for stratum 3 timing applications and conforms to gr-1244-core (issue 2), gr-253-core (issue 3), itu-t g.812 (type 3) and itu-t g813 (option 2). applications include shared port adapters, data digital cross connects, adm's, dslam's, multiservice platforms, switches and routers in tdm, sdh and sonet environments. the sm3-it timing module helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. features ? industrial temp. range (-40 to 85c) small package size, 1.45 x 1.0 x 0.535 inches four auto select input references, 8 khz - 77.76 mhz frequency qualification and loss of reference detection for each input master/slave operation with phase adjustment manual/autonomous operation bi-directional spi port control three cmos frequency outputs - output1 from 12.96 - 77.76 mhz, m/s output @ 8khz, bits @2.048 mhz or 1.544 mhz 3.3v operation sm3-it ultra miniature stratum 3 module 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com bulletin tm064 page 1 of 32 revision 02 date 07 nov 08 issued by eng
data sheet #: tm064 p age 2 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice general description the sm3-it timing module provides a clock output that meets or exceeds stratum 3 specifications given in gr-1244-core (issue 2), gr-253-core (issue 3), itu-t g.812 (type 3) and itu-t g813 (option 2). the sm3-it features four reference inputs that will auto-detect the following reference frequencies: 8 khz, 1.544 mhz, 2.048 mhz, 12.96 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz and 77.76 mhz. the sm3-it timing module can be configured during production to produce an output up to 77.76 mhz. this output is derived from an onboard vcxo and must be specified when ordering. the bits output selectable for either 1.544 or 2.048 mhz. the mas- ter/slave output is 8khz. the user communicates with the sm3-it module through a spi port. the user controls the sm3-it opera- tion by writing to the appropriate registers. the user can also enable or disable spi operation through a spi_enable pin. the sm3-it offers a wide range of options for the system designer. the bandwidth is spi port-selectable from 0.025 hz to 1.6 hz. 0.098 hz is the recommended operational bandwidth for sonet minimum clock and most stratum 3 applications. the 8 khz output has an adjustable pulse width. the pull-in range is also adjustable to establish the desired reference frequency reject ion limits. a free run frequency calibration value can be written to the module to provide a high degree of accuracy in the free r un mode. the reference frequency for any given reference input is automatically detected. a wealth of status information is avai lable through the spi port registers. the user also has a choice between autonomous or full manual control operation. in manual mode, the user controls the module operating modes free run, hold over or locked to a specific reference in normal mode. if the chosen reference is unavailable or disqualified the module automatically enters hold over. in autonomous control mode, operational mode selection occurs automatically based on reference priority and qualification sta- tus. when the active reference becomes disqualified, the module will switch to another qualified reference. if none is availabl e, it will switch to holdover. in the revertive mode the module will seek to acquire the highest priority qualified reference. in the non -revertive mode the module will not return to the previous reference even after it is re-qualified unless there are no other qualified ref erences. switching between references is hitless. likewise, the output frequency slew rate is minimized during any change of operating mode, including entry into and return from free run or hold over to protect traffic from transient-induced bit errors. reference status information and the operating mode information is accessed through status registers. the module will set the interrupt pin (spi_int) low to indicate a status change. an alarm pin is used to indicate failure of the active reference stat us. free run operation guarantees an output within 4.6ppm of nominal frequency and holdover operation guarantees the output frequency will not change by more than 0.37ppm during the first 24 hours. frequency accuracy is based on a tcxo for its small size, low power consumption and outstanding performance over all environmental conditions. the module operates on 3.3v 5% with a typical power drain of less than 1.6w at turn on, dropping to approximately 1w @ room temperature after warming up. the module operates over the -40 to 85 c industrial temperature range. functional block diagram figure 1 reference input monitor control mode reference selection dpll apll reference priority, revertivity and mask ta b l e bus interface eeprom dac ocxo vcxo trst tck tdo tdi tms m/s ref ref 1 - 4 reset master select t1/e1 spi_enbl spi_clk spi_in spi_out spi_int 4 output1 m/s_out bits_clk los lol hold_good
data sheet #: tm064 p age 3 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice specifications for ultra miniature stratum 3 - industrial temperature table 1 parameter specification voltage 3.3v 5% power 1.6w maximum during start up, 1.0w typical @ room temperature operating temp range -40 - 85c reference frequency 1, 2, 3, 4 8 khz - 77.76 mhz (auto detected) cmos output frequency #1 12.96 mhz - 77.76 mhz m/s output 8 khz bits_clk 1.544/2.048 mhz (selectable) master/slave input reference 8 khz - 77.76 mhz input reference pulse width 10 ns min @ 8 khz, 5 ns min @ >8 khz free run accuracy 4.6 ppm hold over stability 0.37 ppm dimensions 1.45 x 1.0 x 0. 535 inches (36.83 x 25.4 x 13.59 mm) pin description table 2 pin # i/o pin name pin description 1 o los alarm output - loss of active reference signal 2 o lol alarm output - loss of lock 3 i m/s ref master/slave reference input ? 8 khz to 77.76 mhz auto detected 4 i ref1 reference input 1 ? 8 khz to 77.76 mhz auto detected 5 i ref2 reference input 2 ? 8 khz to 77.76 mhz auto detected 6 i ref3 reference input 3 ? 8 khz to 77.76 mhz auto detected 7 i ref4 reference input 4 ? 8 khz to 77.76 mhz auto detected 8 tdi jtag tdi pin* 9 tms jtag tms pin* 10 trst jtag trst pin* 11 o bits_clk 1.544 or 2.048 mhz output selected by pin 16 12 o m/s_out master/slave 8 khz output 13 o output1 synchronous primary output 14 i vpp positive programming supply pin. during normal operation it is recommended to float this pin. 15 i vpn negative programming supply pin. during normal operation it is recommended to float this pin. 16 i t1/e1 bits_clk select input ? 1=1.544 mhz, 0=2.048 mhz 17 o hold_good holdover good output flag ? 1=holdover available 18 tdo jtag tdo pin* 19 tck jtag tck pin* 20 gnd module ground 21 i spi_clk spi port clock input 22 i spi_in spi port data input 23 vcc 3.3 vdc vcc supply input 24 i spi_enbl spi port enable input ? active low 25 i reset module reset ? active low, 10 ms hold time 26 o spi_out spi port data output 27 o spi_int spi port interrupt output ? active low 28 i master select master/slave select input ? 1=master, 0=slave
data sheet #: tm064 p age 4 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice register map table 3 address reg name description type 0x00 chip_id_low low byte of chip id r 0x01 chip_id_high high byte of chip id r 0x02 chip_revision chip revision number r 0x03 bandwidth bandw idth select r/w 0x04 ctl_mode manual or automatic selection of op_mode,bits clock output frequency r/w indication, and frame/multi-frame sync pulse width mode control 0x05 op_mode master f ree run, locked, or hold over mode, or slave mode r/w 0x06 max_pullin_range maximum pull-in range in 0.1 ppm units r/w 0x07 m/s ref_activity cross reference activity r 0x08 ref_activity activities of 4 reference inputs r 0x09 ref_pullin_sts in or out of pull-in range of 4 reference inputs r 0x0a ref_qualified qualification status of 4 reference inputs r 0x0b ref_mask availabi lity mask for 4 reference inputs r/w 0x0c ref_available availability of 4 reference inputs r pin diagram figure 2 sm3 1 14 15 los lol m/s ref ref1 ref2 ref3 ref4 tdi tms trst bits_clk m/s_out output1 vpp master selec t spi_int spi_out reset spi_enbl vcc spi_in spi_clk gnd tck tdo hold_good t1/e1 vpn 2 3 4 5 6 7 8 9 10 11 12 13 16 17 18 19 20 21 22 23 24 25 26 27 28 (top view)
data sheet #: tm064 p age 5 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice 0x0d ref_rev_delay reference reversion delay time, 0 - 255 minutes r/w 0x0e phase_offset phase offset between m/s ref & m/s output (for the slave in m/s operation) in 250ps resolution r/w 0x0f calibration local oscillator digital calibration in 0.05 ppm resolution r/w 0x10 fr_pulse_width frame sync pulse width r/w 0x11 dpll_status digital phase locked loop status r 0x12 intr_event interr upt events r 0x13 intr_enable enab le individual interrupt events r/w 0x14 ref1_frq_offset1 ref1 frequency offset in 0.2 ppm resolution r 0x15 ref2_frq_offset2 ref2 frequency offset in 0.2 ppm resolution r 0x16 ref3_frq_offset3 ref3 frequency offset in 0.2 ppm resolution r 0x17 ref4_frq_offset4 ref4 frequency offset in 0.2 ppm resolution r 0x18 reserved 0x19 reserved 0x1a reserved 0x1b reserved 0x1c ref1_frq_priority1 ref1 frequency and priority r/w 0x1d ref2_frq_priority2 ref2 frequency and priority r/w 0x1e ref3_frq_priority3 ref3 frequency and priority r/w 0x1f ref4_frq_priority4 ref4 frequency and priority r/w 0x20 reserved 0x21 reserved 0x22 reserved 0x23 reserved 0x24 freerun prior ity control and priority for designation of free run as a reference r/w 0x25 history_policy sets policy for hol d over history accumulation r/w 0x26 history_cmd save, restore and flush comands for hold over history r/w 0x27 holdover_time indicates the time since entering hold over state r 0x30 cfgdata configuration data write register r/w 0x31 cfgctr_lo configuration data write counter, low byte r 0x32 cfgctr_hi configuration data write counter, high byte r 0x33 chksum configuration data checksum pass/fail indicator r 0x36 ee_wrt_mode disab les/enables writing to the external eeprom r/w 0x37 ee_cmd read/wr ite command & ready indication register for ext. eeprom access r/w 0x38 ee_page_num page n umber for external eeprom access r/w 0x39 ee_fifo_port read/write data for external eeprom access r/w register map continued
data sheet #: tm064 p age 6 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice the sm3-it can accept up to 4 external references from 8 khz to 77.76 mhz and each is monitored for signal presence and frequency offset. additionally, a cross-couple reference input is provided for master/slave operation. reference selection may be manual or automatic, according to pre-programmed priorities. all reference switches are performed in a hitless manner, and frequency r amp controls ensure smooth output signal transitions. when references are switched, the device provides an automatic phase build-ou t to minimize phase transitions in the output clocks. three output signals are provided, the first up to 77.76 mhz , the second fixed at 8 khz for use as a frame sync signal as well as a cross-couple reference for master/slave operation. in slave mode, the output phase may be adjusted from -32 to +31.75ns relativ e to the master, to accommodate downstream system needs, such as different clock distribution path lengths. the third output is a bits c lock, selectable as either 1.544 mhz or 2.048 mhz. device operation may be in free run, locked, or hold over modes. in free run, the clock frequencies are simply determined by th e accuracy of the calibrated internal clock. in locked mode, the sm3-it phase locks to the selected input reference. while locked , a frequency history is accumulated. in hold over mode, the output frequencies are generated according to this history. the digital phase locked loop provides the critical filtering and frequency/phase control that meet or exceed all requirements in critical jitter and accuracy performance parameters. filter bandwidth may be configured to suit applications requirements. control functions are provided via standard spi bus register interface. register access provides visibility into a variety of r egistered information as well as providing extensive programmable control capability. operating modes: the sm3-it operates in either free run, locked, or hold over mode: free run ? in free run mode, output 1, m/s output, and bits_clk , the output clocks, are determined directly from and have the accuracy of the calibrated free running internal clock. reference inputs continue to be monitored for signal presence and frequ ency offset, but are not used to synchronize the outputs. locked ? the output 1, m/s output, and bits_clk , outputs are phase locked and track the selected input reference. upon entering the locked mode, the device begins an acquisition process that includes reference qualification and frequency slew rate limitin g, if needed. once satisfactory lock is achieved, the ?locked? bit is set in the dpll_status register, and a compilation of the frequ ency history of the selected reference is started. when a usable hold over history has been established, the hold_good pin is set, and the ?hold over available? bit is set in the dpll_status register. phase comparison and phase lock loop filtering operations in the sm3-it are completely digital. as a result, device and loop behavior are entirely predictable, repeatable, and extremely accurate. carefully designed and proven algorithms and techniques ensure completely hit-less reference switches, operational mode changes, and master/slave switches. basic loop bandwidth is programmable from .025 hz to 1.6 hz, giving the user a wide range of control over the system response. when a new reference is acquired, maximum frequency slew limits ensure smooth frequency changes. once lock is achieved, (<100 seconds for stratum 3), the ?locked? bit is set. if the sm3-it is unable to maintain lock, loss of lock (lol) is asserted. all transitions between locked, hold over and free run modes are performed with minimal phase events and smooth frequency and phase transitions . reference phase hits or phase differences encountered when switching references (or when entering locked mode) are nulled out with an automatic phase build-out function, with a residual phase error of less than 1ns. hold over ? upon entering hold over mode, the output 1, m/s output, and bits_clk , outputs are determined from the hold over history established for the last selected reference. output frequency is determined by a weighted average of the hold over hist ory, and accuracy is determined by the internal clock. hold over mode may be entered manually or automatically. automatic entry into hol d over mode occurs when operating in the automatic mode, the reference is lost, and no other valid reference exists. the transfer into and out of hold over mode is designed to be smooth and free of hits. the frequency slew is also limited to a maximum of 2 ppm/sec. the history accumulation algorithm uses a first order frequency difference filtering algorithm. typical holdover accumulation takes about 15 minutes. when a usable holdover history has been established, the hold_good pin is set, and the ?holdover available? bit is set in the dpll_status register. the holdover history continues to be updated after ?holdover avaialble? is declared. the algorithm accumulates the holdover history only when it has locked to either an external reference in master operation or t he m/s ref clock in slave operation, starting 15 minutes after power up. tracking will be suspended automatically when switching to a new reference and in hold over or free run mode. a set of registers allows the application to control a holdover history maintenanc e policy, enabling either a re-build or continuance of the history when a reference switch occurs. detailed description
data sheet #: tm064 p age 7 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice detailed description continued the m/s output or the output 1 of each device may be cross-connected to the other device?s m/s ref input. the device auto-detec ts the frequency on the m/s ref input. master or slave state of a device is determined by the m/s pin. thus, master/slave state is always manually controlled by the application. the master synchronizes to the selected input reference, while the slave synchronizes t o the m/s ref input. (note that 8khz frame phase alignment is maintained across a master/slave pair of devices only if m/s output is used as the cross couple signal.) the unit operating in slave mode locks on and phase-aligns to the cross-reference clock (m/s output or output 1) from the unit in master mode. the phase skew between the input cross-reference and the output clock for the slave unit is typically less than 1 ns (under 3ns in dynamic situations, including reference jitter and wander). perfect phase alignment of the two output 1 output clocks would require no delay on the cross-reference clock connection. to accommodate path length delays, the sm3-it provides a programmable phase skew feature. the slave?s output 1 or m/s output may be phase shifted -32ns to +31.75ns relative to m/s input according to the contents of the ms_phase_offset register to compensat e for the path length of the m/s output or output 1 to m/s input connection. this offset may therefore be programmed to exactly compe nsate for the actual path length delay associated with the particular application's cross-reference traces. the offset may further be adjusted to accommodate any output clock distribution path delay differences. thus, master/slave switches with the sm3-it devices may be accomplished with near-zero phase hits. the first time a unit becomes a slave, such as immediately after power-up, its output clock phase starts out arbitrary, and wil l quickly phase-align to the cross-reference from the master unit. the phase skew will be eliminated (or converged to the programmed phas e offset) step by step. the whole pull-in-and-lock process will complete in about 60 seconds. there is no frequency slew protecti on in slave mode. in slave mode, the unit's mission is to lock to and follow the master. once a pair of units has been operating in aligned master/slave mode, and a master/slave switch occurs, the unit that becomes master will maintain its output clock phase and frequency while a phase build-out (to the current output clock phase) is perfor med on its selected reference input. therefore, as master mode operation commences, there will be no phase or frequency hits on the clock output. likewise, the unit that becomes the slave will maintain its output clock frequency and phase for 1 msec before starting to foll ow the cross-reference, protecting the downstream clock users during the switch. assuming the phase offset is programmed for the actua l propagation delay of this cross-reference path, there will again be no phase hits on the output clock of the unit that has tran sitioned from master to slave. master / slave configuration figure 3 stc3500 sm3 m/s output / output1 m/s output / output1 m/s ref refs1-4 refs1-4 m/s ref 2 sm3 1 furthermore, under register access control, a backup holdover history register is provided. it may be loaded from the active ho ldover history or restored to the active holdover history. the active holdover history may also be flushed. holdover mode may be entered at any time. if there is no holdover history available, the prior output frequency will be maintai ned. when in holdover, the application may read (via register access) the time since holdover was enterred. master/slave operation pairs of sm3-it devices may be operated in a master/slave configuration for redundant timing source applications. a typical configuration is shown below.:
data sheet #: tm064 p age 8 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice detailed description continued serial communication the user can control the operation of the sm3-it module through the spi port. timing diagrams are shown below. this interface is only for point-to-point applications. serial interface timing, read access figure 4 1 2 3 4 a0 a1 a2 a3 a4 a5 a6 5 6 7 8 13 14 15 16 9 10 11 12 0 d0 lsb msb d1 d2 d3 d4 d5 d6 d7 msb lsb t drdy t ch t cl t cs t rws t rwh spi_enable spi_clk spi_in spi_out serial interface timing, write access figure 5 spi_enable spi_clk spi_in t rws 1 2 3 4 a0 a1 a2 a3 a4 a5 a6 5 6 7 8 13 14 15 16 9 10 11 12 1 t rwh lsb msb t ch t cl t cs d0 d1 d2 d3 d4 d5 d6 d7 lsb msb spi_out note: spi_out is normally held at logic 0 except when tri-stated during an address read cycle on the spi_in pin or when data is being output on the spi_out pin.
data sheet #: tm064 p age 9 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice reference input quality monitoring each reference input is monitored for signal presence and frequency offset. signal presence for the ref1-4 inputs is indicated in the ref_activity register and signal presence for the m/s ref is indicated in bit 0 of the m/s ref_activity register. the frequency offset between the ref1-4 inputs and the calibrated local oscillator is available in the ref_frq_offset registers (4). register ref_pullin_sts indicates, for each of the ref1-4 inputs, if the reference is within the maximum pull-in range. the maximum pull-in range is indicated in register max_pullin_range , and may be set in 0.1ppm increments. typically, it would be set according to the values specified by the standards (gr-1244) appropriate for the particular stratum of operation. the ref_qualified register contains the ?anded? condition of the ref_activity and ref_pullin_sts registers for each of the ref1-4 inputs, qualified for 10 seconds. when a reference signal has been present for > 10 seconds and is within the pull-in range, it ?s bit is set. the ref_available register contains the ?anded? condition of the ref_qualified register and the ref_mask register, and therefore represents the availability of a reference for selection when automatic reference and operational mode selection is enabled. reference input selection, frequencies, and mode selection one of four reference input signals ( ref 1-4 ) are selected for synchronization in master mode (as below in the op_mode register description. 0x05). ref1-4 may each be 8 khz, 1.544 mhz, 2.048 mhz, 12.96 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz or 77.76 mhz. reference frequencies are auto-detected (frequency determined by the chip) and the detected frequency can be read from the ref_frq_priority registers (see register descriptions and operation section). active reference and operational mode selection may be manual or automatic, as determined by bit 1 in the ctl_mode register. in manual mode, register writes to op_mode select the reference and mode. the m/s ref input for slave operation is frequency auto-detected and may be 8khz, 1.544mhz, 2.048mhz, 12.96mhz, 19.44mhz, 25.92mhz, 38.88mhz, 51.84mhz or 77.76mhz. signal presence and frequency for the m/s ref input is indicated in bits 0-3 of the m/s ref_activity register. active reference and operational mode selection may be manual or automatic, as determined by bit 1 in the ctl_mode register. in manual mode, register writes to op_mode select the reference and mode. the reset default is manual mode. in automatic mode, the reference is selected according to the priorities written to the four ref_frq_priority registers. individual references may be masked for use/non-use according to the ref_mask register. a reference may only be selected if it is ?available? - that is, it is qualified, as indicated in the ref_qualified register, and is not masked (see reference input quality monitoring and register descriptions and operation sections). furthermore, bit 3 of each ref_frq_priority register will determine if that reference is revertive or non-revertive. when a reference fails, the next highest priority ?available? (signal present, non-masked, and acceptable frequency offset) reference will be se lected. when a reference returns, it will be switched to only if it is of higher priority and the current active reference is marked ?revert ive?. additionally, the reversion is delayed according to the value written to the ref_rev_delay register (from 0 to 255 minutes). detailed description continued serial interface timing table 4 symbol par ameter minimum nominal maximum units notes t cs spi_enable low to spi_clk low 15 - - ns t ch spi_clk high time 25 - - ns t cl spi_clk low time 25 - - ns t rws read/write setup time 15 - - ns t rwh read/write hold time 15 - - ns t drdy data ready - - 25 ns t hld data hold 15 - - ns t cstri chip select to data tri-state 5 - - ns t csmin minimum delay between successive accesses300 - - ns
data sheet #: tm064 p age 10 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice detailed description continued the automatic reference selection is shown in the following state diagram: the operational mode is according to the following state diagram: no available reference and no hold over history ref loss w/no good hold over history and no other available reference automatic reference selection figure 6 automatic operational mode selection figure 7 locked on ref n select & lock on ref m ref n returns, ref m marked ?non-revertive? locked on ref m time for t= ref_rev_delay ref_rev_delay time expired loss of ref n select new reference: qualified (within max. pull-in range, signal present > 10 sec.), non-masked ref n returns, ref m marked ?revertive? next highest priority, stay ref return ref loss w/good hold over history and no alternate reference available ref loss w/alternate reference available return ref ref loss w/no good hold over history and no other available reference no available reference and no hold over history reference available locked hold over free run (select highest priority) higher priority ref return with prior reference marked ?revertive?
data sheet #: tm064 p age 11 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice detailed description continued output signals and frequency output 1 is the primary output, and in locked mode is synchronized to the selected reference. output 1 must be specified at the time of ordering as any one of the following frequencies : 12.96 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz or 77.76 mhz. m/s output is an 8 khz output available as a frame reference or synchronization signal for cross-coupled pairs of sm3-it devices operated in master/slave mode. in master mode, m/s output is synchronized to the selected reference. in slave mode, m/s output is in phase with the m/s ref offset by the value written to the phase_offset register (+31.75 to -32ns, with .25ns resolution). m/s output may be a 50% duty cycle signal, or variable high-going pulse width, as determined by the ctl_mode and fr_pulse_width registers. in variable pulse width mode, the width may be from 1 to 15 multiples of the output 1 cycle time. see register descriptions and op eration section. bits_clk is the bits clock output at either 1.544 mhz or 2.048 mhz. it is selected by the t1/e1 input and its state may be read in bit 3 of the ctl_mode register. when t1/e1 = 1, the bits frequency is 1.544 mhz, and when t1/e1 = 0, the bits frequency is 2.048 mhz. this output clock is digitally synthesized from output1 directly and will be synchronized to m/s output. interrupts the sm3-it module supports eight different interrupts and appears in intr_event (0x12) register. each interrupt can be individually enabled or disabled via the intr_enable (0x13 ) register. each bit enables or disables the corresponding interrupt from asserting the spi_int pin. interrupt events still appear in the intr_event (0x12) register independent of their enable state. all interrupts are cleared once intr_event (0x12) register is read. the interrupts are: any reference changing from available to not available any reference changing from not available to available m/s ref changing from activity to no activity m/s ref changing from no activity to activity dpll mode status change reference switch in automatic reference selection mode loss of signal loss of lock interrupts and reference change in autonomous mode interrupts can be used to determine the cause of a reference change in autonomous mode. let us assume that the module is currently locked to ref1 . the module switches to ref2 and spi_int pin is asserted. the user reads the intr_event (0x12) register. if the module is operating in autonomous non-revertive mode, the cause can be determined from bits 4, 5, 6 and 7. bit 5 is set to indicate active reference change. if bit 6 is set then the cause of the reference change is loss of active reference. if bit 7 is set then the cause of the reference change is a loss of lock alarm on the active reference. if the module is operating in autonomous revertive mode, the cause can be determined from bits 1, 4,5, 6 and 7. bit 5 is set to indicate active reference change. if bit 6 is set then the cause of the reference change is loss of active reference. if bit 7 is set th en the cause of the reference change is a loss of lock alarm on the active reference. if bit 1 is set then the cause of the reference change is the availability of a higher priority reference. note : the dpll mode status change bit (bit 4) is also set to indicate a change in dpll_status (0x11) register, during an interrupt caused by a reference change. the data in dpll_status (0x11) register however is not useful in determining the cause of a reference change. this is because bits 0-2 of this register always reflects the status of the current active reference and hence cannot b e used to determine the status of the last active reference. interrupts in manual mode in manual operating mode, when the active reference fails due to a loss of signal or loss of lock alarm, an interrupt is genera ted. for example, in case of a loss of signal, bits4 and 6 of intr_event (0x12) register would be set to indicate loss of signal and dpll mode status change. the user may choose to read the dpll_status (0x11) register, though in manual mode bit6 of i ntr_event (0x12) register is a mirror of bit0 of dpll_status (0x11) register. this holds true for a loss of lock alarm, where bit7 of intr_event (0x12) register is a mirror of bit1 of dpll_status (0x11) register. internal clock calibration the internal clock may be calibrated by writing a frequency offset v.s. nominal frequency into the calibration register. this c alibration is used by the synchronization software to create a frequency corrected from the actual internal clock output by the value writ ten to the calibration register. see register descriptions.
data sheet #: tm064 p age 12 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice register descriptions and operation chip_id_low, 0x00 (r) bit 7 ~ bit 0 low byte of chip id: 0x12 chip_id_high, 0x01 (r) bit 7 ~ bit 0 high byte of chip id: 0x30 chip_revision, 0x02 (r) bit 7 ~ bit 0 chip revision number: 0x02 bandwidth_pbo, 0x03 (r/w) bit 7 ~ bit 5 bit 4 bit 3 ~ bit 0 reserved reserved bandwidth selection in hz: 0:default 0000: 0.025 0001: 0.025 0010: 0.025 0011: 0.025 0100: 0.025 0101: 0.025 0110: 0.049 0111: 0.098(reset default) 1000: 0.20 1001: 0.39 1010: 0.78 1011 - 1111: 1.6 bits 3 - 0 select the phase lock loop bandwidth in hertz. the reset default is 0.098 hz. ctl_mode, 0x04 (r/w) bit 7 ~ bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved default: 0 m/s output bits clock hm ref: active reserved pulse width output 0: register control ref erence control: f requency: of op mode/ref selection: 0: 50% 1: 1.544 mhz (will always 1: manual 1: controlled by 0: 2.048 mhz be 0) 0: automatic fr_pulse_width (read only) default: 1 register default: 0 when bit 1 is reset (automatic reference and mode selection), bits 3 - 0 of the op_mode register become read-only. the power-up default for bit 1 = 1 for manual reference selection and default for bit 4 = 0 for 50% duty cycle on m/s output.
data sheet #: tm064 p age 13 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice register descriptions and operation continued op_mode, 0x05 (r/w) bit 7 ~ bit 5 bit 4 bit 3 ~ bit 0 reserved master or sla v e mode free run, locked, or hold over: 1: master 0000: free run mode 0: slave 0001: locked on ref1 (read only) 0010: locked on ref2 0011: locked on ref3 0100: locked on ref4 0101 - 1000: not used 1001 - 1111: hold over max_pullin_range, 0x06 (r/w) bit 7 ~ bit 0 maximum pull-in range in 0.1 ppm unit this register should be set according to the values specified by the standards (gr-1244) appropriate for the particular stratum of operation. the power-up default value is 10 ppm. (= 4.6ppm aging + 4.6 ppm pullin + margin). m/s_activity, 0x07 (r) bit 7 ~ bit 4 bit 3 ~ bit 0 reserved cross ref erence activity 0000: no signal 0001: 8khz 0100: 12.96mhz 0101: 19.44mhz 0110: 25.92mhz 0111: 38.88mhz 1000: 51.84mhz 1001: 77.76mhz 1010-1111: reserved indicates signal presence and auto-detected frequency for the m/s ref input. ref_activity, 0x08 (r) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ref4 activity ref3 activity ref2 activity ref1 activity 0: off 0: off 0: off 0: off 1: on 1: on 1: on 1: on 0: off 0: off 0: off 0: off each bit indicates the presence of a signal for that reference. when the device is in slave mode, it will lock to the m/s ref , independent of the values written to bits 3 - 0 of the op_mode register. the operational mode and reference selection written to bits 3 - 0 while in slave mode will, however, take effect whe n the device is made the master. when bit 1 of the ctl_mode register is reset (automatic reference and mode selection) and the device is in master mode, bits 3 - 0 of the op_mode register become read-only.
data sheet #: tm064 p age 14 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice register descriptions and operation continued ref_pullin_sts, 0x09 (r) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0: default 0: default 0: default 0: default ref4 sts ref3 sts ref2 sts ref1 sts 1: in range 1: in range 1: in range 1: in range 0: out range 0: out range 0: out range 0: out range each bit indicates if the reference is within the frequency range specified by the value in the max_pullin register. ref_qualified, 0x0a (r) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0: default 0: default 0: default 0: default ref4 qual: ref3 qual: ref2 qual: ref1 qual: 1: avail. 1: avail. 1: avail. 1: avail. 0: not avail. 0: not avail. 0: not avail. 0: not avail. this register contains the ?anded? condition of the ref_activity and ref_pullin_sts registers for each of the ref1-4 inputs, quali- fied for 10 seconds. when a reference signal has been present for > 10 seconds and is within the pull-in range, it?s bit is set . ref_mask, 0x0b (r/w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0: default 0: default 0: default 0: default ref4 mask: ref3 mask: ref2 mask: ref1 mask: 1: avail. 1: avail. 1: avail. 1: avail. 0: not avail. 0: not avail. 0: not avail. 0: not avail. default: 0 default: 0 default: 0 default: 0 individual references may be marked as ?available? or ?not available? for selection in the automatic reference selection mode (bit 1 = 0 in the ctl_mode register). the reset default value is 0, ?not available?. in manual reference selection, either hardware or register controlled, the reference masks have no effect, but do remain valid and are applied upon a transition to automatic mod e. ref_available, 0x0c (r) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0: default 0: default 0: default 0: default ref4 avail: ref3 avail: ref2 avail: ref1 avail: 1: avail. 1: avail. 1: avail. 1: avail. 0: not avail. 0: not avail. 0: not avail. 0: not this register contains the ?anded? condition of the ref_qualified and ref_mask registers. ref_rev_delay, 0x0d (r/w) bit 7 ~ bit 0 reference reversion delay time, 0 - 255 minutes. default, 0000 0101, 5 minutes in automatic reference selection mode, when a reference fails and later returns, it must be available for the time specified in the ref_rev_delay register before it can be switched back to as the active reference (if the new reference was marked as ?revertive ?). see figure 7.
data sheet #: tm064 p age 15 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice register descriptions and operation continued *note: only references 1 - 4 are used with this model phase_offset, 0x0e (r/w) bit 7 ~ bit 0 the 2?s complement value of phase offset between master output module and slave output module, ranges from -32 ns to +31.75 ns positive value: master output rising edge leads slave output negative value: master output rising edge lags slave output in slave mode, the slave?s outputs may be phase shifted -32ns to +31.75ns in .25ns increments, relative to the master module ac - cording to the contents of the phase_offset register, to compensate for the path length of the master to slave connection. if a phase offset is used, then the two sm3-it devices would typically be written to the appropriate phase offset values for th e re- spective path lengths of each master to slave connection, to ensure that the same relative output signal phases will persist through master/slave switches. calibration, 0x0f (r/w) bit 7 ~ bit 0 2?s complement value of local oscillator digital calibration in 0.05 ppm resolution to digitally calibrate the free running clock synthesized from the internal clock, this register is written with a value corres ponding to the known frequency offset of the oscillator from the nominal center frequency. fr_pulse_width, 0x10 (r/w) bit 7 ~ bit4 bit 3 ~ bit 0 reserved pulse width for m/s clock output, 1-15 multiples of the sync_clk clock period. bits 4 and 5 of the ctl_mode register determine if the m/s 8 khz output is 50% duty cycle or pulsed (high going) outputs. when they are pulsed, the fr_pulse_width register determines the width. width is the register value multiple of the sync_clk clock pe- riod. valid values are 1 - 15. reset default is 0001. writing to 0000 maps to 0001. dpll_status, 0x11 (r) bit 7 ~bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved hold ov er hold ov er loc k ed loss of loc k loss of signal build a v ailab le 1: locked 1: loss of lock 1: no activity complete 1: avail. 0: not locked 0: no loss of lock on active 1: complete 0: not avail. reference 0: incomplete 0: active ref- erence signal present bit 0 indicates the presence of a signal on the selected reference. bit 1 indicates a loss of lock (lol). loss of lock will be asserted if lock is not achieved within the specified time for the s tratum level of operation, or lock is lost after being established previously. lol will not be asserted for automatic reference switches. bit 2 indicates successful phase lock. it will typically be set in <100 seconds for stratum 3 with a good reference. it will in dicate ?not locked? if lock is lost. bit 3 indicates if a hold over history is available. bit 4 indicates when a new hold over history has been sucessfully built and transferred to the active hold over history.
data sheet #: tm064 p age 16 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice register descriptions and operation continued intr_event, 0x12 (r) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loss of loss of active refer- dpll mode m/s ref m/s ref any refer- any refer- lock signal ence change status change from change from erence change erence change change no activity to activity to no from not from available activity activity available to able to not available available interrupt state = 1. when an enabled interrupt occurs, the spi_int pin is asserted, active low. all interrupts are cleared and the spi_int pin pulled high when the register is read. reset default is 0. intr_enable, 0x13 (r/w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 enable inter- enable inter- enable inter- enable inter- enable inter- enable inter- enable inter- enable inter- rupt event 7: rupt event 6: rupt event 5: rupt event 4: rupt event 3: rupt event 2: rupt event 1: rupt event 0: 1: enable 1: enable 1: enable 1: enable 1: enable 1: enable 1: enable 1: enable 0: disable 0: disable 0: disable 0: disable 0: disable 0: disable 0: disable 0: disable default: 0 default: 0 default: 0 default: 0 default: 0 default: 0 default: 0 default: 0 enables or disables the corresponding interrupts from asserting the spi_int pin. interrupt events still appear in the intr_event reg- ister independent of their ?enable? state. reset default is interrupts disabled. ref(1-4)_frq_offset, 0x14 ~ 0x17(r) bit 7 ~ bit 0 2?s complement value of frequency offset between reference and calibrated local oscillator, 0.2ppm resolution these registers indicate the frequency offset, in 0.2ppm resolution, between each reference and the local calibrated oscillator . 0x14 - 0x17 correspond to ref1 - ref4 . ref(1-4)_frq_priority, 0x1c ~ 0x1f (r/w) bit 7 ~ bit 4 bit 3 bit 2 ~ bit 0 f requency re v er tivity pr ior ity 0000: none 1: revertive 0: highest 0001: 8 khz 0: non-revertive 3: lowest 0010: 1.544 mhz default: 0, default: 0 0011: 2.048 mhz non revertive 0100: 12.96 mhz 0101: 19.44 mhz 0110: 25.92 mhz 0111: 38.88 mhz 1000: 51.84 mhz 1001: 77.76 mhz 1010-1111: reserved bits 2 - 0 indicate the priority of each reference for use in automatic reference selection mode (bit 1 of the ctl_mode register =0). in manual reference selection mode (bit 1 of the ctl_mode register = 1), these bits are read-only and will contain either the reset de- fault or values written when last in automatic reference selection mode. for equal priority values, lower reference numbers hav e higher priority. bit 3 specifies if the reference is revertive or non-revertive in automatic reference selection mode. when a reference fails, t he next highest priority ?available? (signal present, non-masked, and acceptable frequency offset) reference will be selected. when a r efer- ence returns, it will be switched to only if it is of higher priority and the current active reference is marked ?revertive?. bits 7 - 4 indicate the auto-detected frequency for each reference. invalid frequencies may result in erroneous device operatio n. if there is no activity on a reference, bits 7-4will be = 0000. bits 7-4 are read only. 0x1c - 0x1f correspond to ref1 - ref4 .
data sheet #: tm064 p age 17 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice freerun_priority, 0x24 (r/w) bit 7 - bit 5 bit 4 bit 3 bit 2 - bit 0 enable/ revertivity priority disable 1: enable 0: highest reserved 1: enable 0: disable 3: lowest 0: disable default: 0 default: 0 default: 0 non-revertive free run may be treated like a reference. when it is enabled, free run will be entered when all references of higher priority are lost or masked. if or when a higher priority reference returns, it is switched to if free run is set as ?revertive?. when disabled , free run will be entered only if manually selected or all references fail without an available hold over history. for equal priority va lue, free run will be treated as lower priority. history_policy, 0x25 (r/w) bit 7 - bit 1 bit 0 reference switch hold over hisory policy reserved 0: rebuild 1: continue bit 0 determines if hold over is retained or rebuilt when a reference switch occurs. see application notes, holdover history accumulation and management section. history_cmd, 0x26 (r/w) bit 7 - bit 2 bit 1-0 hold over histroy commands 01: save active history to backup history reserved 10: restore active history from backup 11: flush the active history and accumulation register 00: no command - use to write bit4 to change policy bits 0-1 are written to save a holdover history to the backup history, restore the active holdover history from the backup, or flush the active history. the default value of the register is 00. the last command is latched and may be read by the application. a flush does not affect the backup history. see application notes, holdover history accumulation and management section. holdover_time, 0x27 (r) bit 7 - bit 0 indicates the time since entering the hold over state. from 0-255, one bit per hour. zero in non-hold over state and stops at 2 55. cfgdata, 0x30 (r/w) bit 7 - bit 0 configuration data write register. configuration data is written to this register. internal use only. cfgctr_lo, 0x31 (r) bit 7 - bit 0 configuration data write counter low byte. low order byte of configuration data write counter. internal use only. register descriptions and operation continued
data sheet #: tm064 p age 18 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice cfgctr_hi, 0x32 (r) bit 7 - bit 0 configuration data write counter high byte. high order byte of configuration data write counter. internal use only. chksum, 0x33 (r/w) bit 7 - bit 1 bit 0 configuration data checksum pass/fail indicator reserved 0: fail 1: pass checksum verification register for configuration data. internal use only. ee_mode, 0x36 (r/w) bit 7 - bit 1 bit 0 eeprom write enable reserved 0: disable 1: enable eeprom write enable register. ee_cmd, 0x37 (r/w) bit 7 bit 6 - bit 2 bit 1 - bit 0 eeprom read/write eeprom read/write command bits: ready bit: 00 = reset fifo 0 = not ready reserved 01 = write command 1 = ready 10 = read command eeprom read/write command register. ee_page_num, 0x38 (r/w) bit 7 - bit 0 eeprom read/write page number, 0x00 to 0x9f (0 - 159) eeprom read/write page number register. eeprom consist of 160 pages. ee_fifo_port, 0x39 (r/w) bit 7 - bit 0 eeprom read/write fifo data. eeprom read/write fifo port register. eeprom data is written to/read from this location. register descriptions and operation continued
data sheet #: tm064 p age 19 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice performance definitions jitter and wander ? jitter and wander are defined respectively as ?the short-term and long-term variations of the significant instants of a digital signal from their ideal positions in time?. they are therefore the phase or position in time modulations of a digi tal signal relative to their ideal positions. these phase modulations can in turn be characterized in terms of their amplitude and frequency. jitte r is defined as those phase variations at rates above 10hz, and wander as those variations at rates below 10hz. fractional frequency offset and drift ? the fractional frequency offset of a clock is the ratio of the frequency error (from the nominal or desired frequency) to the desired frequency. it is typically expressed as (n parts in 10 x ), or (n x 10- x ). drift is the measure of a clock?s frequency offset over time. it is expressed the same way as offset. time interval error (tie) ? tie is a measure of wander and is defined as the variation in the time delay of a given signal relative to an ideal signal over a particular time period. it is typically measured in ns. tie is set to zero at the start of a measurement, a nd thus represents the phase change since the beginning of the measurement. maximum time interval error (mtie) ? mtie is a measurement of wander that finds the peak-to-peak variations in the time delay of a signal for a given window of time, called the observation interval ( t ). therefore it is the largest peak-to-peak tie in any observation interval of length t within the entire measurement window of tie data. mtie is therefore a useful measure of phase transients, maximum wander and frequency offsets. mtie increases monotonically with increasing observation interval. time deviation (tdev) ? tdev is a measurement of wander that characterizes the spectral content of phase noise. tdev( t is the rms of filtered tie, where the bandpass filter is centered on a frequency of 0.42/ t . sm3-it performance input jitter tolerance ? input jitter tolerance is the amount of jitter at its input a clock can tolerate before generating an indication of improper operation. gr-1244 and itu-813 requirements specify jitter amplitude v.s. jitter frequency for jitter tolerance. the s m3-it device provides jitter tolerance that meets the specified requirements. input wander tolerance ? input wander tolerance is the amount of wander at its input a clock can tolerate before generating an indication of improper operation. gr-1244 and itu-813 requirements specify input wander tdev vs. integration time as shown belo w. integration time, (seconds) tdev (ns) 0.05 < 10 100 10 < < 1000 31.6 x 0.5 1000 n/a the sm3-it device provides wander tolerance that meets these requirements. phase transient tolerance ? gr-1244 specifies maximum reference input phase transients that a clock system must tolerate without generating an indication of improper operation. the phase transient tolerance is specified in mtie(ns) v.s. observation time fr om .001 to 100 seconds, as shown below. observation time s (seconds) mtie (ns) 0.001326 s < 0.0164 61,000 x s 0.0164 < s < 1.97 925 + 4600 x s 1.97 s 10,000 the sm3-it will tolerate all reference input transients within the gr-1244 specification. free run frequency accuracy ? free run frequency accuracy is the maximum fractional frequency offset while in free run mode. it is determined by the accuracy of the internal clock. hold over frequency stability ? hold over frequency stability is the maximum fractional frequency offset while in hold over mode. it is determined by the stability of the internal clock. performance specifications
data sheet #: tm064 p age 20 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice performance specifications continued wander generation characteristics ? mtie wander generation ? wander generation is the process whereby wander appears at the output of a clock in the absence of input wander. the sm3-it wander generation characteristics, mtie and tdev, are shown below, along with the requirements masks (bandwidth = 0.098 hz): 1 10 100 1000 0.1 1 10 100 1000 10000 100000 observation time (sec) mtie (ns) gr-1244-core, r5-5 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 10000 100000 integration time (sec) tdev (ns) gr-1244-core, r5-4 wander generation characteristics ? tdev
data sheet #: tm064 p age 21 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice phase transients ? a phase transient is an unusual step or change in the phase-time of a signal over a relatively short time period. this may be due to switching between equipment, reference switching, diagnostics, entry or exit to/from hold over, or input ref erence transients. the sm3-it performance for reference switches is shown below: performance specifications continued wander transfer ? wander transfer is the degree to which input wander is attenuated (or amplified) from input to output of a clock. the gr-1244 requirements for wander transfer limits are shown below. integration time, (seconds) stratum 3 tdev (nanoseconds) < 0.05 n/a 0.05 < 0.1 1020 x 0.1 < 1.44 102 1.44 < 10 102 10 < 300 32.2 x 0.5 300 1000 32.2 x 0.5 1000 < n/a the sm3-it, when configured for the appropriate stratum 3 bandwidth frequency, meets the stratum 3 requirements, jitter generation ? jitter generation is the process whereby jitter appears at the output of a clock in the absence of input jitter. the device jitter generation performance is as shown below: jitter 19.44 mhz 77.76 mhz broadband 8 ps typical 8 ps typical (10 hz - 2 mhz) sonet band (12 khz -2mhz) (12 khz -20mhz) 5 ps typical 1.5 ps typical jitter transfer ? jitter transfer is the degree to which input jitter is attenuated (or amplified) from input to output of a clock. it is a function of the selected bandwidth. phase transients ? mtie 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 1000 observation time (sec) mtie (ns) gr-1244-core, r5-14
data sheet #: tm064 p age 22 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice performance specifications continued capture range and hold range ? capture range and hold range are the maximum frequency errors on the reference input within which the phase locked loop is able to achieve lock and hold lock, respectively. the sm3-it stratum 3 performance is shown belo w: characteristic sm3-it requirement capture range 50 ppm maximum gr-1244-core, sec 3.4 hold range 50 ppm maximum gr-1244-core, sec 3.4 this is the minimum capability, and guarantees the ability to capture and lock with a reference that is offset the maximum allo wed in one direction in the presence of a clock that is offset the maximum in the opposite direction (4.6 ppm + 4.6 ppm = 9.2 ppm). master/slave skew and reference switch settling time ? master/slave skew and reference switch settling time performance are shown below: characteristic sm3-it requirement master/slave phase skew < 2 ns n/a reference switch settling time stratum 3: < 100 sec. up to 20 ppm stratum 3: < 100 sec. up frequency offset to +/- 4.6 ppm frequency offset sm3-it initialization: power-up: 1. if possible, always start up in master mode. after the module is powered up, hold the reset pin low for 10ms. wait 1200ms a nd read the contents of register 0x33. if it reads1 then the module came up properly. if it reads 0 then reset the module and re-r ead register 0x33 after 1200ms. the contents of 0x33 must read 1 before continuing. 2. remain in the default free-run mode for 10 seconds then read the value of bit 1 of register 0x11 or pin 2, the lol alarm out put. if the lol alarm is set, the reset pin must be pulled low as in 1 above. in the free-run mode the lol alarm should never be se t. this indicates the module is in an invalid state. if there is no lol alarm in free-run the module is ready. operation: on power up or after a reset all the registers are loaded with their default values. the default values of some important regis ters are given below assuming the module operates as a master address(hex) register name v alue(binary msb first) notes 0x03 bandwidth_pbo 00000111 bandwidth = 0.098hz 0x04 ctl_mode 0000r010 r - read only 0x05 op_mode 00010000 indicates free run mode 0x06 max_pullin_range 01100100 0x0b ref_mask 00000000 0x0d ref_rev_delay 00000101 0x0e phase_offset 00000000 0x0f calibration 00000000 0x11 dpll_status 00000000 indicates no active refer ence 0x13 intr_enable 00000000 indicates interrupts are disabled 0x1c-0x1f ref(1-4)_frq_priority xxxx0000 f requencies are auto detected 0x33 chksum xxxxxxx1 bit0 should be high to indicate that data has been loaded correctly from the eeprom.
data sheet #: tm064 p age 23 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice i. the unit starts up in free run and operates in manual mode. here are the steps that need to be taken to lock the unit to a reference in manual mode. 1. apply signal to the reference inputs. 2. set the appropriate pull in range by writing to address 0x06. 3. a value of 0001xxxx, depending on which (ref 1-4) reference to lock to, should be written to address 0x05. 4. enable reference mask for appropriate references by writing a 1 to the reference bit in address 0x0b. 5. enable all interrupts by writing 1111 to address 0x13. ii. to lock the unit to a reference in autonomous (automatic) mode after power up or reset, the following steps should be take n. you can also switch from manual to autonomous mode directly. when doing so, please ensure that the appropriate references are available by checking ref_available register (address: 0x0c). 1. clear bit1 of ctl_mode register (address: 0x04). this puts the module in autonomous mode. 2. apply signal to the reference inputs 3. set the appropriate pull in range by writing to address 0x06 4. enable reference mask for appropriate references by writing a 1 to the reference bit in address 0x0b. 5. set priority and revertivity for the input references by writing to the appropriate ref_frq_priority registers (bits 3-0). 6. enable all interrupts by writing 1111 to address 0x13. 7. set the unit to operate in autonomous mode by clearing bit1 of address 0x04 iii. slave mode operation: 1. as a slave, the module operates in autonomous mode. 2. the bandwidth is set, by default, to 1.6hz (bandwidth_pbo register (address 0x03): 00001011). 3. note that bit 4 of the op_mode register (address 0x05) is cleared. 4. the values in bits 3-0 of this register have no effect on the operation of the slave module. 5. for the slave module to track the master accurately, an appropriate phase offset value should be written to phase_offset register (address 0x0e) is used to compensate for the path delay. 6. the module will lock to the cross reference input (xref) from the master. iv reset parameters: 1. the reset pin should be held low for a minimum of 10 milliseconds to ensure a complete reset occurs. 2. the spi interface should not be accessed for a minimum of 1200ms after the reset pin is de-asserted. switching master/slave designations: the following steps need to be taken before making master module a slave and vice versa. 1. copy the value in the phase_offset register (address 0x0e) of the slave to the master module's phase_offset regsiter (address 0x0e). 2. read the contents of bits 3-0 of the master's op_mode register (address 0x05) and copy it into bits 3-0 of the slave's op_mode register (address 0x05). 3. it is recommended that the contents of ref(1-4)_frq_priority registers (address 0x1c-0x1f) and ref_mask register (address 0x0b) from master be copied to slave to ensure seamless master/slave switches. master/slave switches should be performed with minimal delay between switching the states of each of the two devices.
data sheet #: tm064 p age 24 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice application notes acceptable output frequencies are: 12.96 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz or 77.76mhz. the device will autodetect the output frequency. reference inputs ? the application may supply up to 4 reference inputs, applied at input pins ref1 - 4 . they may each be 8 khz, 1.544 mhz, 2.048 mhz, 12.96 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz or 77.76 mhz. the device auto-detects the reference frequencies, and they may be read from the ref(1-4)_frq_priority registers in register control mode, as described in the control mode sections that follow. reference switches are performed in a hitless manner. however, if the application externally changes the frequency of a partic ular reference, the device requires 20ms to auto-detect the new frequency. manual switches to a frequency changed reference should not be made during this interval. automatic reference selection mode accounts for the auto-detection in the reference qualification. references would typically (but need not be) connected in decreasing order of usage priority. for example if redundant bits clo cks are available, they would typically be assigned to ref1 and ref2 , with other transmission derived signals following thereafter. master/slave operation ? for some applications, reliability requirements may demand that the clock system be duplicated. the sm3-it device will support the master/slave duplicated configuration for such applications. to facilitate it?s use, the device includes the necessary signal cross coupling and control functions. redundancy for reliability implies two major considerations: 1) maintain ing separate failure groups such that a failure in one group does not affect it?s mate, and 2) physical and logical partitioning fo r repair, such that a failed component can be replaced while the mate remains in service, if so desired. system design needs to account to mee t system level goals. master / slave configuration figure 8 stc3500 sm3 master/slave output m/s ref ref4 ref1 #2 sm3 #1 m/s ref master/slave output synchronized clock output synchronized clock output ref1 ref4 ref1 ref4 m/s_out output1 bits_clk output1 m/s_out bits_clk bits clock output bits clock output
data sheet #: tm064 p age 25 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice application notes continued master/slave configuration ? a pair of devices are interconnected by cross-coupling their respective m/s outputs or output1 to the other device?s m/s ref input (see figure 8). additionally, the reference inputs for each device would typically be correspondingly the same, so that when a master/slave switch occurs, synchronization would continue with the same reference. the references may be driven by the same signal directly or via separate drivers, as the redundancy of that part of the system requires. distribution path lengths are not critical here, as a phase build-out will occur when a device switches from slave to master. the path lengths of the two m/s output to m/s ref signals is of interest, however. they need not be the same. however, to accommodate path length delays, the sm3-it provides a programmable phase skew feature, which allows the application to offset t he output clock from the cross-reference signal by -32ns to +31.75ns. this offset may therefore be programmed to exactly compensa te for the actual path length delay associated with the particular application?s cross-reference traces. the offset may be further adj usted to accommodate any output clock distribution path delay differences. phase offset is programmed by writing to the phase_offset reg ister, and is typically a one-time device initialization function. (see register description and register access control sections). th us, master/ slave switches with the sm3-it devices may be accomplished with near-zero phase hits. for applications that use hardware control only (i.e. phase offset programming is not available), it is desirable to keep the c ross couple path lengths at a minimum and relatively equal in length, as the path length will appear as a phase hit in the slave clo ck output when a master/slave switch occurs in a hardware control configuration. master/slave operation and control ? the master/slave state is always manually controlled by the application. master or slave state of a device is determined by the master select pin. choosing the master/slave states is a function of the application, based on the configuration of the rest of the system and potential detected fault conditions. when operating in hardware control or register access manual control mode, it is important to set the slave reference selection the same as the master to ensure use of the same reference when/if the slave becomes master. in register access manual control mod e, the ref_mask register should also be written to the same value for both devices. master/slave switches should be performed with minimal delay between switching the states of each of the two devices. this can be easily accomplished, for example, by controlling the master/slave state with a single signal, coupled to one of the devices thr ough an inverter. in the case of register access automatic control mode, where reference selection is automatic, it is necessary to read the operational mode bits 3-0) from the master?s op_mode register and write it to the slave?s op_mode register. the master?s reference selection will then be used by the slave when it becomes master. in addition to having the references populated the same, and i n the same order for both devices, it is desireable to write the reference frequency and priority registers ref(1-4)_frq_priority and the ref_mask registers to the same values for both devices to ensure seamless master/slave switches. reset ? device reset is an initialization time function, which resets internal logic and register values. a reset is performed automatically when the device is powered up. registers return to their default values, as noted in the register descriptions. d evice mode and functionality following a reset are determined by the state of the various hardware control pins. holdover history accumulation and maintenance -- holdover history accumulation and maintenance may be controlled in greater detail if register bus access to the device is provided. holdover history accumulation and control encompasses three device int ernal registers, three bus access registers for control and access, and two status bits in the dpll_status register. once lock has been achieved, holdover history is compiled in the accumulation register. it is transferred to the active holdove r history when it is ready (typically in about 15 minutes). the ?holdover available? bit and output pin are set to ?1?. from then on, the active holdover history is continually updated and kept in sync with the holdover history accumulation register. (see figure 11). hold over history accumulation register active hold over history backup hold over history
data sheet #: tm064 p age 26 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice hold over history access and control registers table 5 register register name description 0x25 history_policy sets policy for hold over history accumulation: ?rebuild? or ?continue? 0x26 history_cmd save, restore, and flush commands for hold over history 0x27 holdover_time indicate s the time since entering the hold over state 0x11 dpll_status bits 3 and 4: hold over available? and ?hold over build complete? build history hold control = 0 hold available = 0 acquire reference hold control = 0 hold available = 0 locked, history complete hold control =1 hold available = 1 acquire reference hold control = 0 hold available = 1 build history hold control = 0 hold available = 1 reference switch reference switch reference switch reference switch reference switch reference lock (with "continue" set) reference lock (with "rebuild" set) reference lock flush flush flush history build complete history build complete, replace active hold over history history restored from backup, re-start the building procedure. hold over history and status states figure 9 application notes continued
data sheet #: tm064 p age 27 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice whenever holdover is entered, it is the active holdover history that is used to determine the holdover frequency. the history_ cmd register allows the application to issue three holdover history control commands: 1) save the active holdover history to the backup history. 2) restore a backup history to the active. 3) flush the active history as well as the accumulation register. the backup history remains intact. both the active and the backup holdover histories are loaded with the calibrated freerun synthesizer control data on reset/powe r-up. the application might use the ?save to backup? in a situation where, for example, the primary reference is known to be of highe r quality than any secondary references, in which case it may be desirable to save and then restore the holdover history accumula ted on the primary reference if the primary reference is lost and holdover is entered upon loss of a secondary reference. users can re store the history from backup any time, even while operating in holdover mode. the frequency transient will be smooth and continuous. it is the responsibility of application software to keep track of the age and viability of the holdover backup history. given time and te mperature effects on oscillator aging, the application may wish to periodically perform a ?save? of the active history to keep the backup current. when switching to a new reference, the active holdover history will remain intact and marked as ?holdover available? (if it was available before the reference switch) until a new history is accumulated on the new reference (typically 15 minutes after lock has been achieved). during the new history accumulation, the ?holdover build complete? bit is reset. once the new history accumulation i s complete, it is transferred to the active history and the ?holdover build complete? bit is set. the active history will then co ntinue to be updated to track the reference. the history_policy register allows the application to control how a new history is built. when set to ?rebuild?: 1) history accumulation begins when lock is achieved on the new reference. 2) the holdover history is rebuilt (taking about 15 minutes). the active history remains untouched until it is replaced when th e build is complete. when the policy is set to ?continue?: 1) if there is no ?available? active history, a new build occurs, as under the ?rebuild? policy. 2) if there is an ?available? active history, it will continue, the accumulation register will be loaded from the active history, and the ?build? process is essentially completed immediately following lock on the new reference. the ?continue? policy may be used by the application if, for example, it is known that the reference switched to may be traced to the same source and therefore likely has no frequency offset from the prior reference. in that case, the ?continue? policy avoids t he delay of rebuilding the holdover history. if the switch is likely to be between references with known or unknown frequency offset, then it is preferable to use the ?rebuild? policy. the time since the holdover state was entered may be read from the holdover_time register. values are from 0 to 255 hours, limi ted at 255, and reset to 0 when not in the holdover state. boundary scan ieee1149.1-2001 (limited testability support) - this module exposes a boundary scan chain which contains one or more boundary scan testable ieee1149.1-2001 complaint devices. the exposed boundary scan chain is ieee1149.1-2001 compliant, and supports all documented testing modes of devices contained within chain. integration of this module into an exi sting boundary scan chain will require the following. - substitution of modules footprint with provided testability model schematic. - modified net list will need to be loaded into boundary scan test vector generation software. testability model schematic and bsdl file(s) can be obtained directly from factory. control modes the device can in turn be operated in a manual control mode, or automatic control and reference selection mode. reset may be pulled low for a minimum of 100ns during sm3-it start-up (or any other desired time) to initialize the full device state . however, power-up will also perform a reset, so in a minimal configuration, reset input may be tied high. the bits clock output frequency is selected by the t1/e1 pin. when t1/e1 = 1, the bits frequency is 1.544 mhz, and when t1/e1 = 0, the bits frequency is 2.048 mhz. master select - determines the master or slave mode. set to ?1? for a master, and ?0? for a slave. master/slave switches should be performed with minimal delay between switching the states of each of the two devices. this can be easily accomplished, for e xample, by controlling the master/slave state with a single signal, coupled to one of the devices through an inverter. for simplex operation, the device should be in master mode - set master select to ?1?. application notes continued
data sheet #: tm064 p age 28 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice mechanical dimensions figure10 .850 [21.59mm] .075 [1.91mm] .125 [3.17mm] 1.450 [36.83mm] max. .018 [.45mm] .535 [13.59mm] max. .100 [2.54mm] .070 [1.78mm] 1.000 [25.40mm] max. pin 1 indicator 0.000 1.050 hole/pad size (28 places): 1. unsocketed module: 0.028" dia. plated hole with 0.060" dia. pad. 2. socketed module: 0.038" dia. plated hole with 0.070" dia. pad. note: for compatibllity with both the unsocketed and socketed modules, connor-winfield recommends using a 0.038" dia. plated hole with 0.070" dia. pad 0.100 0.950 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 0.000 1.500 pin 1 top view keep out area customer component footprint dimensions figure 11 application notes continued
data sheet #: tm064 p age 29 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice required external components 1. place series resistors (33 ohms) on all reference inputs (pins 4 - 7). 2. place series resistors (33 ohms) on spi_in and spi_clk inputs (pins 21, 22). 3. place one .01uf and one 47-100uf capacitor at the input power pin (pin 23). 4. one 4.7uf (25v) capacitor is required at the vpp pin (pin 14). 5. one 4.7uf (25v) capacitor is required at the vpn pin (pin 15). pcb layout recommendations 1. orient module so airflow is parallel along the header strips (pins). 2. place de-coupling and/or filter components as close to module pins as possible. 3. do not place any components directly beneath the module on the topside of the host pcb. 4. ensure that only clean and well-regulated power is supplied to the module. 5. isolate power and ground inputs to the module from noisy sources. 6. provide power and ground connections through a 0.050" wide trace (minimum) using 1-oz. cu or equivalent copper feature (i.e. internal plane, copper area fill, etc.). 7. keep module signals away from sensitive or noisy analog and digital circuitry. 8. avoid split ground planes as high-frequency return currents may be affected. 9. allow extra spacing between traces of high-frequency inputs and outputs. 10.keep all traces as short as possible - avoid meandering trace paths. 11.avoid routing signals directly beneath the module on the topside of the host pcb. 12.if possible, provide a copper area directly beneath the module on the topside of the host pcb. connect this copper area to ground. 13.it is recommended that the connections of the jtag, vpp and vpn pins be routed to pads, preferably in a sil pattern as shown in figure 13 below. it is recommended to use 0.1? center to center spacing. optional socket mounting recommendations mating sockets may be used if permanent installation of the sm3-it module is not desired. two possible sources for these sockets include: 1. samtec, "low profile socket strips", sl series, pn sl-114-g-19. (http://www.samtec.com/) 2. mill-max, "single-in-line sockets", 315 series, pn 315-xx-114-41-001. (http://www.mill-max.com/) the sm3-it requires two 14-pin sockets. the optional dual footprint configuration shown in figure 13 requires one 14-pin and two 16-pin sockets. application notes continued 18 v pp v pn gnd tck tdi tdo tms rck figure 13
data sheet #: tm064 p age 30 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice optional sm3-it/sm3e dual footprint sm3 sm3e 1 14 15 los lol m/s ref ref1 ref2 ref3 ref4 tdi tms trst bits_clk m/s_out output1 vpp ref5 ref6 master selec t spi_int spi_out reset spi_enbl vcc spi_in spi_clk gnd tck tdo hold_good t1/e1 vpn ref7 ref8 2 3 4 5 6 7 8 9 10 11 12 13 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0.850" 1.100" (top view) a dual footprint configuration may be used when designing a host circuit board containing the connor winfield sm3-it or sm3e modules. the smaller sm3-it contains a subset of the signal pins found on the larger sm3e in locations which allow for a simpl e dual footprint arrangement like the one shown in figure 13. the modules shown in figure 13 are arranged in a left-justified fashion. notice that right justified or center justified (with an additional column of sm3-it pins) arrangements are also possible, depending on the designer's preference. placement of external components 1. place series resistors (33 ohms) on all reference input (sm3-it pins 4 - 7, sm3e pins 4-7 & 15-18). 2. place series resistors (33 ohms) on spi_in and spi_clk inputs (sm3-it pins 21,22, sm3e pins 25 & 26). 3. place one .01uf and one 47-100uf capacitor at the input power pin (sm3-it pin 23, sm3e pin 27). 4. one 4.7uf (25v) capacitor is required at the vpp pin (sm3-it & sm3e pin 14). 5. one 4.7uf (25v) capacitor is required at the vpn pin (sm3-it pin 15, sm3e pin 19). be sure to consult connor winfield's respective datasheets for additional mechanical, electrical, footprint and keep-out inform ation. figure 12 application notes continued
data sheet #: tm064 p age 31 of 32 rev: 02 date: 11/07/08 ? copyright 2008 the connor-winfield corp. all rights reserved specifications subject to change without notice ordering information sm3-it-xxx.xxm replace xxx.xx with one of the following available frequencies, 012.96mhz, 019.44mhz, 025.92mhz, 038.88mhz, 051.84mhz or 077.76mhz. the inclusion of ?g? indicates that this product is rohs compliant. please contact connor-winfield for other frequencies that may be available . similar products from connor-winfield sm3g-xxx.xxm - stratum 3 module with 4 input references. sm3-8rg-xxx.xxm - stratum 3 module with 8 input references. sm3eg-xxx.xxm - stratum 3e module with 8 input references.
2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com revision revision date note 00 08/23/04 final release data sheet 01 10/15/07 add initialization info, pg. 22-23 02 11/07/08 added input pulse width spec to table 1

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